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Lattice Semiconductor
CSIX-to-PI40 IP Core User’s Guide
The basic PI40 cell structure and CSIX Cframe structure are shown in Tables 2 and 3, respectively. PI40 cells have
a ?xed, parameterizable payload length that may be set to 64, 72 or 80 bytes in length. CSIX Cframes have a vari-
able, parameterizable maximum length that may be set between 0 and 256 bytes. CSIX speci?es that a Traf?c
Manager (TM) shall support a programmable MAX_FRAME_PAYLOAD_SIZE parameter between 1 and 256 bytes
and that fabrics shall support Cframe sizes of any size equal to or less than the maximum value speci?ed for
MAX_FRAME_PAYLOAD_SIZE. CSIX also speci?es that system integrators should use the smaller of the maxi-
mum values for MAX_FRAME_PAYLOAD_SIZE speci?ed by the TM and fabric being integrated. The CSIX/PI40
Bridge is parameterizable to support PI40 cell size and CSIX MAX_FRAME_PAYLOAD_SIZE as speci?ed in
Table 5.
Table 3. PI40 Cell Structure
Cell Component
Link Header
Switch Header
PI40 Payload
BIP
Table 4. CSIX Cframe Structure
Cframe Component
Base Header
Extension header
CSIX Payload
Vertical Parity
Size
1 byte
11 bytes
64, 72 or 80 bytes
1 byte
Size
2 bytes
0-4 bytes
Variable
2 bytes
Table 5. CSIX/PI40 Bridge Payload Parameter
CSIX Maximum Payload Size
64 bytes
72 bytes
80 bytes
PI40 Payload Size
(MAX_FRAME_PAYLOAD_SIZE)
56 bytes
64 bytes
72 bytes
Data Flow
Ingress (CSIX-to-PI40) Direction Data Flow
Cframes received at the CSIX interface are loaded into a FIFO in the CSIX-L1 core. The CSIX-L1 core supports
two FIFOs, one for data and one for control Cframes. The only control Cframes presently de?ned are ?ow control
Cframes. In the CSIX/PI40 Bridge application, no ?ow control Cframes are received at the CSIX interface, so only
the data FIFO is implemented in the ingress direction.
Cframes are read from the ingress data FIFO by the IFI and converted to PI40 cells as shown in Figure 3. Each
Cframe is mapped to a separate PI40 cell.
6
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